Page 48 - 2024S

UEC Int’l Mini-Conference No.52 41

An Efficiency Method Accelerating Number Theoretic Transform in

Post-quantum Cryptography on RISC-V SoC

Duc-Thuan DAM , Trong-Thuc HOANG, Cong-Kha PHAM
∗
Department of Computer and Network Engineering
The University of Electro-Communications
Tokyo, Japan

Keywords: RISC-V, NTT, PQC, Kyber, Dilithium, Accelerator.

Abstract
Post-quantum cryptography was introduced to counter the attacks of quantum computers, which
cause the insecurity of current cryptography. Among the selected algorithms, three out of four are
lattice-based, namely Kyber, Dilithium, and Falcon. One of the most time-consuming transformations
in lattice-based cryptography (LBC) algorithms is the number theoretic transform (NTT), present in all
stages, including key generation, encryption, decryption, and authentication. Therefore, we proposed
an accelerator for NTT on the Rocket RISC-V SoC platform to speed up the software implementing the
above algorithms. The accelerator architecture is designed and evaluated on the FPGA before being
attached to the bus on an SoC architecture; the CPU will perform the entire algorithm in software, in
which the NTT computation is performed on hardware by sending data and control instructions down
the data bus. At that point, the accelerator will act as a peripheral. The results show that the efficiency
achieved increased from 71.5 % to 99.3 % compared to other software running on the RISC-V platform
and up to 77.5 % compared to the previous result with the same hardware/software method.

∗
The author is supported by (SESS) MEXT Scholarship.