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UEC Int’l Mini-Conference No.53                                                               51






              A 20 MHz Input Frequency 4 GHz Cascade Fractional-N PLL with

                                        Multi-Phase Multi-Frequency


                            Thi Viet Ha NGUYEN , Trong-Thuc Hoang, Cong-Kha Pham
                                                     ∗
                                    Department of Computer and Network Engineer
                                       The University of Electro-Communications
                                                      Tokyo, Japan


             Keywords: Phase-Locked Loop, inductor-less, phase noise, high frequency.



                                                        Abstract
                    This paper presents a fractional-N Phase-Locked Loop (PLL) using an inductor-less voltage-
                 controlled oscillator (VCO) and a digital delta-sigma modulator for 5G and high-frequency applica-
                 tions. Operating with a 20 MHz reference frequency, the synthesizer achieves a 10 MHz bandwidth,
                 significantly suppressing the phase noise of its constituent ring oscillators. Fabricated in 180-nm
                 CMOS technology, the design demonstrates an in-band phase noise of -101.5 dBc/Hz and an inte-
                 grated jitter of 1.89 ps rms .















































               ∗
                The author is supported by (MICH) MEXT Scholar-
             ship.
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